The present disclosure relates to a flip-flop, and more particularly, to a flip-flop which transmits a scan input and data for scan-testing a semiconductor circuit.
Device for testability (DFT) technologies used to test a semiconductor chip are widely used to maintain the quality of the semiconductor chip. Scan test technology, which is one of the DFT technologies, is an old technology, but still plays an important role in chip testing technology.
A flip-flop stores and sequentially transmits received signals in response to a clock signal or a pulse signal. A flip-flop having a scan input receives a test scan signal and outputs a test scan signal so as to test a logic circuit unit in a semiconductor circuit. Such a flip-flop having a scan input provides an easy test of the logic circuit unit.
FIG. 1 is a circuit diagram illustrating a conventional flip-flop 100 having a scan input.
Referring to FIG. 1, the conventional flip-flop 100 includes a multiplexer 110, which receives a data signal D and a scan input signal SI, and a master slave flip-flop 120. The multiplexer 110 includes a first AND gate 111, which receives and performs an AND operation on the data signal D and an inversed scan enable signal SEB, a second AND gate 112, which receives and performs an AND operation on the scan input signal SI and a scan enable signal SE, and a first NOR gate 113, which performs a NOR operation on outputs of the first AND gate 111 and the second AND gate 112.
The master slave flip-flop 120 includes a first tri-state inverter 121, which inverts and then outputs an output of the first NOR gate 113 when an inversed clock signal CKB is logic high, first latch units 122, 123, which latch an output of the first tri-state inverter 121 in response to a clock signal CK and the inversed clock signal CKB, a second tri-state inverter 124, which inverses and then outputs an output of the first latch units 122, 123 when the inversed clock signal CKB is logic high, second latch units 125, 126, which latch an output of the second tri-state inverter 124 in response to the clock signal SK and the inversed clock signal CKB, and an inverter 127, which inverses and then outputs an output of the second latch units 125, 126.
When the scan enable signal SE is logic low, the data signal D is output through the first AND gate 111 and the first NOR gate 113. When the clock signal CK is logic low, the data signal D is transmitted to the first latch units 122, 123. When the clock signal CK is logic high, the first tri-state inverter 121 is turned off and the data signal D is stored in the first latch units 122, 123. The second tri-state inverter 124 inverses the data signal D stored in the first latch units 122, 123, as the data signal D is synchronized with a next clock signal CK in logic low, and transmits the inversed data signal D to the second latch units 125, 126. The data signal D stored in the second latch units 125, 126 is transmitted to a logic circuit unit of a semiconductor chip via the inverter 127. The second latch units 125, 126 maintain stored data until the data is synchronized with a next clock signal.
However, since the conventional flip-flop 100 having such a structure must include the multiplexer 110 at an input terminal of the flip-flop 100, the setup time by the multiplexer 110 remarkably increases. Also, the master slave flip-flop 120 using a master slave method has a long input-to-output delay (i.e., the delay time from input to output), and thus the conventional flip-flop 100 is not suitable for high speed use.